8 - 9 OCTOBER 2018 | workshop

Exascale computing workshop: experiences and best practices for porting applications to emerging HPC architectures and platforms

PART 1 - PLATFORM ARCHITECTURE | 8 OCTOBER 2018

14.00 – 14.20 John Goodacre, University of Manchester

Welcome and introduction to Exascale Projects

14.20 – 14. 40 Yong Qin, HPC Advisory Council

The Effect of In-Network Computing-Capable Interconnects on the Scalability of CAE Simulations

14.40 – 15.00 Peter Hopton, Iceotope

Hardware and Architecture

15.00 – 15.20 Nikos Kossifidis, FORTH

Bring-up and boot environment of HPC multi-node daughter board

15.20 – 15.40 Gino Perna, EnginSoft

Exascale system challenges: system software integration and application management

Coffee break 15.40 - 16.10

16.10 – 16.30 Manolis Ploumidis, FORTH

Software developer's view of UNIMEM Platforms

16.30 – 16.50 Kyunghum Kim, Barcelona Supercomputing Centre

Clusters and MPI

16.50 – 17.10 Konstantin Bakanov, Queen's University of Belfast

Automatic Scheduling of OpenCL Tasks in a Cluster Environment

17.10 – 17.30 Dirk Koch, Manchester University

The Role of FPGA Design Tools and Partial Reconfiguration in ECOSCALE

PART 2 - SYSTEM SOFTWARE APPLICATIONS | 9 OCTOBER 2018

09.30 – 09.50 Arslan Arif, Politecnico di Torino

Performance and energy-efficient implementation of a smart city application on FPGAs

09.50 – 10.10 Manolis Ploumidis, FORTH

Experiences from porting MPI on the ExaNeSt platform

10.10 – 10.30 Mike Ashworth, Manchester University

LFRIC weather application

10.30 – 10.50 Martin Kersten, MonetDB Solutions

Vanishing barriers in big data management technology for application development

Coffee break 10.50 - 11.20

11.20 – 11.40 Dirk Pleiter, Jülich Supercomputing

Scaling scientific applications towards exascale

11.40 – 12.00 Francesco Simula, INFN

Towards Real-time cortical simulations: energy and interconnect scaling on distributed systems

12.00 – 12.20 Tom Vander Aa, IMEC

Virtual Molecule Screening on FPGA: First Experiments

12.20 – 12.40 Luca Tornatore, INAF

Porting Astrophysical Applications on Exascale platforms

The international race to develop the world’s first exascale supercomputer is the next frontier in High Performance Computing (HPC). An exascale computer is one that can complete one quintillion (10¹⁸) Floating Point Operations Per Second (FLOPS). This represents a thousand-fold improvement over today’s petascale machines which can achieve one quadrillion (10¹⁵) flops. One exaflop (Eflops), therefore, equals 1000 petaflops (pflops)¹.
But the creation of an exascale supercomputer requires substantial changes to the current technological models, including in the areas of energy consumption, scalability, network topology, memory, storage, resilience and, consequently, the programming models and systems software – none of which can scale to these performance levels.

Architecturally, existing petascale machines mainly deliver power through multi-core accelerators (Graphics Processing Units (GPUs), Cell Broadband Engine Architecture (Cell) processors, etc.), which have already created challenges for scientific applications. These stumbling blocks will become more evident in future exascale systems as millions of processing units cause parallel application scalability issues (due to sequential application parts having to synchronise their communications) and other bottlenecks.

This means that after the hardware and platforms, applications and systems software for exascale supercomputers need to be redesigned in order to exploit these numbers of computing units more efficiently.

This workshop aims to provide a forum for vanguard users and developers in the HPC arena to share their experiences and achievements around the various European platforms developed by the ExaNeSt, ExaNoDe, Ecoscale and EuroExa projects.

Whether you are designers of new hardware architectures or system components; software or application developers; or users that need to exploit these massive processing capacities, everyone has something valuable to contribute to the discussion in the development of this next frontier of HPC.

All these pioneering experiences provide vital information and perspectives on problems, solutions and challenges to software and hardware developers in the HPC sphere. This feedback is fundamental to assisting the efforts to make these architectures and platforms more widely available to the scientific and technological communities in the next several years, and to secure the economic, technological, scientific and industrial benefits that supercomputing potentially offers to the global challenges facing the world today.

1. See https://kb.iu.edu/d/apeq